With the reduction in feature size and the ever-increasing speed of complementary metal-oxide-semiconductor (CMOS) logic circuitry, low-k dielectric/copper integration schemes are becoming increasingly more attractive. Complimentarily, the back-end-of-line (BEOL) processing aspects of advanced integration schemes are becoming a more integral part of the overall system. Devices and functions which were once part of the chip package may now be incorporated into the chip using BEOL processing, in response to cost and performance demands. One such device, which provides a cost and performance advantage and can be incorporated onto the semiconductor chip using BEOL processing, is a decoupling capacitor.
On-chip decoupling capacitors in semiconductor integrated circuit devices are needed to dampen power/ground bounce in high-speed digital systems. This power/ground bounce phenomenon results from resonance effects in the power supply circuitry. In addition, it is further understood that on-chip decoupling capacitors reduce or eliminate the effect of electromagnetic or radiative interference effects.
The present invention addresses the design of on-chip decoupling capacitors and their compatibility with the new low-k dielectric materials being used for advanced CMOS logic process flows. Low-k dielectric materials are simply dielectric materials having a dielectric constant (k) of less than about 4. Conventional methods for manufacturing semiconductor devices are incompatible with the use of low-k dielectric materials, unless additional masking layers, with associated increases in process complexity and costs, are used.
When forming a decoupling capacitor during BEOL processing in a low-k dielectric/copper integration scheme, several factors must be considered. Decoupling capacitors are vertically stacked with a lower electrode connected to a subjacent copper wire which is typically used as an interconnect. Low-k dielectric materials are used as the dielectric material in which damascene copper interconnect wires are formed because of the low parasitic capacitance between adjacent conductive wires, such as copper, when using a low-k dielectric material. Thus, the use of a low-k dielectric material in the damascene processing scheme allows for a maximum degree of integration because adjacent copper lines may be placed in close proximity to one another.
Complexity arises out of the fact that the low-k dielectric materials are typically carbon-based or includes carbon. Photoresist films commonly used as masking materials, in all patterning operations, are also carbon-based. Therefore, processes that are used to strip the photoresist materials also attack the exposed low-k dielectric materials. Poor selectivity in the etch processes used to etch the capacitor dielectric and tantalum nitride (TaN) film commonly used in capacitor electrodes creates additional problems. For example, during the etching process used to remove the capacitor dielectric from the lower TaN electrode, the lower TaN electrode may be attacked. Furthermore, during the etching process used to remove the lower TaN electrode from the low-k carbon-based dielectric material, the underlying low-k carbon-based dielectric material may be further attacked. After the etching process is complete, the stripping process used to remove the photoresist film severely attacks the underlying low-k dielectric and therefore degrades device integrity. Another issue using this integration scheme is copper-to-copper shorting. When the underlying structure includes damascene copper wires formed within a low-k dielectric material, shorting between the exposed copper wires may result during reactive ion etching (RIE) processes due to the back-sputtering of the exposed underlying copper metal.
In summary, there is a need to provide a structure and process for forming the structure which allow for the formation of vertically stacked decoupling capacitors over a damascene structure including tightly packed copper interconnect wires formed within a low-k dielectric material.